1. Field of the Invention
The present invention relates to a semiconductor device having field effect transistors, and a method for manufacturing the semiconductor device.
2. Related Art
“Silicon large-scale integrated circuit” is one of the fundamental device technologies that will support the advanced information society in the future. High performances through highly advanced features, high-speed operations, low power consumptions, and the likes, have been realized with minute semiconductor devices such as CMOS (Complementary Metal Oxide Semiconductor) logic devices and flash memories. In recent years, however, it has been difficult to attain high performances with minute devices, due to various physical limitations.
With the conventional gate electrodes formed with silicon in CMOS logic devices, there have been such problems as the increasing gate parasitic resistance observed with the higher device operation speed, the decreases of the effective capacitances of insulating films due to the carrier depletion at the interfaces with the insulating films, and the variations in threshold voltage due to the added impurities spreading into the channel regions. To solve those problems, a metal gate technique has been developed. By the metal gate technique, the conventionally employed silicon is replaced with a heat-resistant metal material, so as to collectively solve the problems such as the increasing gate parasitic resistance, the capacitance decreases due to depletion, and the spread of impurities. However, the metal gate technique causes great concern about the complicated device manufacturing process.
To eliminate such concern, a full-silicidation technique (hereinafter referred to also as the FUSI (Fully Silicided Gate) technique) has been developed. By the full-silicidation technique, a CMOS transistor is formed by a conventional silicon gate technique, and the silicon gate is then chemically reacted with a metal (silicidation). As a result, the silicon gate is turned into a silicide, and thus a metal gate is obtained. This technique has a tremendous application, because a metal gate can be formed while the gate processing and post oxidization can be performed by the conventional silicon gate technique.
The advantage of the FUSI technique is that the effective work function of a silicide can be modulated by controlling the type and amount of the impurity element to be added to the silicon gate prior to silicidation. When silicidation is performed, the impurities added to the silicon gate are segregated at the interface between the gate insulating film made of SiO2 and the silicide, due to a so-called “snow-plowing effect”. The original work function of the silicide material is modulated by the effect of the segregated impurities. More specifically, in a case of a p-channel MIS transistor, the work function of the silicide is increased by a material such as boron or aluminum segregated at the interface. In a case of an n-channel MIS transistor, the work function of the silicide is reduced by a material such as phosphorus, arsenic, or antimony segregated at the interface. Accordingly, the threshold voltages (Vth) of both transistors can be readily set at desired values.
Meanwhile, as for the gate insulating film, it is necessary to introduce a high-k material having a high dielectric constant, so as to restrain an increase in device power consumption due to an increase in leakage current. It has been believed that a combination of the FUSI technique and a high-k material is inevitable in future products, and provides CMOS logic devices of higher performance. In reality, however, the flat band voltage Vfb of a silicide/high-k material behaves very differently from that of a conventional gate insulating film, because of the specific properties of the interface between a silicide and a high-k material. As a result, there has been a report that controlling the threshold voltages Vth of a MOS transistor becomes very difficult (see K. Takahashi et al., “Dual Work Function Ni-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45 nm-node LSTP and LOP Devices”, p.p. 91-94, IEDM, (2004) (hereinafter referred to as Document 1)). When the material of an insulating film is switched from SiO2 to a high-k material, the apparent work function of the silicide decreases, and the effect of work function modulation by the impurities is lost.
A CMOS logic device of higher performance cannot be formed with a FUSI/high-k combination, unless the problem of the difficulty in controlling the threshold voltages Vth is solved. There has been a report that an SiO2 layer provided at the interface between a silicide and an insulating film made of a high-k material can correct an abnormal shift of the flat band voltage Vfb. According to this report, HfO2 is used as the material of a high-k film, and nickel silicide (NiSi) is used as a silicide. However, the work function of NiSi also decreases as in the case of SiO2, and the effect of work function modulation by impurities such as phosphorus and boron is substantially lost, as mentioned in Document 1. As a result, it becomes difficult to obtain desired threshold voltages Vth.
Meanwhile, there has also been a report that increases in work function can be obtained as in the case where the gate insulating film is made of SiO2. According to this report, a SiO2 layer of 1.1 nm in thickness is provided at the interface between NiSi and HfO2, and silicidation is performed after BF2 ions are implanted into the silicon gate (see C. F. Huang and B. Y. Tsui, “Analysis of NiSi Fully-Silicided Gate on SiO2 and HfO2 for CMOS Application”, p.p. 506-507, SSDM, (2005) (hereinafter referred to as Document 2)). However, the reason that such an effect can be achieved is not discussed in Document 2.
Document 2 discloses a structure in which a material such as SiO2 having a low dielectric constant is stacked together with a high-k film. Such a structure disclosed in Document 2 is not very suitable for practical use, since the capacitance of the gate insulating film is severely reduced, leading to the inhibition of high-speed operations of a CMOS logic device.
Meanwhile, to form a high-functioning stack-type memory cell (substrate/tunnel insulating film/floating gate electrode/interelectrode insulating film/control gate electrode, for example) to be used for a flash memory or the like, it is effective to change the control gate electrode from the conventional n+-polysilicon to a metal gate. By doing so, the depletion layer in the silicon gate disappears, and the voltage drop caused in the depletion layer can be ignored. Accordingly, the voltage of the control gate electrode can be effectively used by performing charge writing/erasing in the floating gate electrode. More specifically, the memory window width of the threshold voltage Vth becomes larger, and a multi-value operation can be easily performed.
As in a case of a CMOS logic device, the control gate electrode is preferably formed with a material that exhibits high compatibility with the conventional LSI process. Therefore, a stack-type memory cell is formed by the conventional polysilicon gate technique, and the polysilicon in the control gate is silicided in the back-end process according to the FUSI technique, which is now a preferred technique.
Another request with respect to the properties of the control gate electrode is a largest possible work function. If the work function is maximized, the leakage current in the interelectrode insulating film at the time of writing can be reduced, and accordingly, the Vth memory window can be made larger.
As for the interelectrode insulating film, on the other hand, there has been a request for greater electric coupling between the control gate electrode and the floating gate electrode while the leakage current is maintained low. This request can be satisfied by employing a high-k material. Particularly, as the miniaturization of memory cells will reach the limit in the near future, the change in cell shape from a three-dimensional one to a flat one is inevitable. In a flat-type memory cell, the capacitance of the interelectrode insulating film can be most effectively increased by polarization in the insulating film. The use of a high-k material for the interelectrode insulating film is inevitable in this technical trend.
As described above, a material having a large work function can be most effectively used as the control gate electrode of a stack-type memory cell, according to the FUSI technique compatible with the conventional LSI manufacturing process. As for the interelectrode insulating film, a high-k material is desirable. However, as in the case of a CMOS logic device, it is not easy to set a large work function for a silicide, due to the specific properties of the interface between the silicide and the high-k film. As already mentioned in the description of the example case with NiSi, the work function of NiSi decreases only because the material of the insulating film is switched from SiO2 to a high-k material. Even if boron or aluminum is segregated at the interface so as to increase the work function, the modulation effect by the impurities is substantially lost due to the specific properties of the interface between NiSi and the high-k film.